Logic Synthesis and SOC Prototyping: RTL Design using VHDLКНИГИ » АППАРАТУРА
Название: Logic Synthesis and SOC Prototyping: RTL Design using VHDL Автор: Vaibbhav Taraate Издательство: Springer Год: 2020 Формат: true pdf/epub Страниц: 251 Размер: 25.2 Mb Язык: English
This book describes RTL design, synthesis, and timing closure strategies for SOC blocks. It covers high-level RTL design scenarios and challenges for SOC design. The book gives practical information on the issues in SOC and ASIC prototyping using modern high-density FPGAs. The book covers SOC performance improvement techniques, testing, and system-level verification. The book also describes the modern Xilinx FPGA architecture and their use in SOC prototyping. The book covers the Synopsys DC, PT commands, and use of them to constraint and to optimize SOC design. The contents of this book will be of use to students, professionals, and hobbyists alike.
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Logic Synthesis and SOC Prototyping: RTL Design using VHDL 
